The present invention relates to a testing device for a semiconductor element or a semiconductor device. More particularly, the invention relates to a method for manufacturing a substrate used to inspect the semiconductor element, which substrate constitutes the inspecting device, in order to realize a semiconductor element inspecting device capable of performing efficient inspection for the electric characteristic of the semiconductor element in a semiconductor manufacturing process, such as wafer probing inspection, burn-in inspection carried out in a wafer state or the like.
The process of manufacturing a semiconductor device, such as an IC, an LSI or the like, is largely divided into two stages: a pre-process including steps up to the formation of an integrated circuit on the surface of a silicon wafer; and a post-process including steps up to the separation of the silicon wafer into individual chips and the sealing of these chips with resins, ceramic or the like.
In a given stage during the pre-process, inspection is carried out for the electric characteristic of each circuit in such semiconductor device to determine if there are any defective chips by a chip unit.
With regard to the electric characteristic inspection, there are generally two available methods. One is probing inspection designed to determine whether or not a good conduction state has been established between circuits. The other is burn-in inspection designed to identify a defect in an accelerated manner by applying thermal or electrical stress on the circuit at a high temperature of about 150xc2x0 C.
Both of the probing inspection and the burn-in inspection employ basically similar means for connecting the wafer to be inspected with an external inspection system, and a method for mechanically pressing individual conductive microprobes to respective electrode pads made of aluminum alloy or other alloys, patterned at a pitche set in the range of several tens to a hundred and several tens xcexcm on the wafer to be inspected, and having a square set in the range of several tens to a hundred and several tens xcexcm and a thickness of about 1 xcexcm.
Conventionally, there has been disclosed a method for inspecting a bare chip by using an inspection tray in JP-A-04-56244. According to the method disclosed therein, a projected electrode (bump) is formed on the electrode pad of the bare chip by plating or the like, and the bare chip is aligned with a burn-in substrate having special solder pasted thereon, and then mounted on the substrate by means of reflowing. The substrate including the bare chip is then set in a burn-in furnace, and burn-in inspection is carried out to determine whether or not the bare chip is defective.
The foregoing inspection tray method includes the steps of, for carrying out inspection: forming a projected electrode on the electrode pad of each bare chip; aligning the bare chip with the substrate and then fixing the chip by means of reflowing; and removing the bare chip from the substrate after the burn-in inspection. These steps greatly complicate the entire process, resulting in the problem of a long time expended to complete the inspection. This problem inevitably brought about an increase in manufacturing costs. In addition, it is necessary to arrange and then align individual bare chips on and with the substrate. However, the alignment of the chips at pitches of several tens xcexcm is difficult and, therefore, such a bare chip inspection method is not suitable for inspecting the semiconductor element, higher integration being expected therefor in the future.
The present invention is made with the foregoing problems in mind, which have been inherent in the electric characteristic inspection of the semiconductor element. It is an object of the invention to provide an inexpensive and highly reliable semiconductor device capable of simultaneously inspecting all the electrode pads of, for example several tens of chips to be inspected en block, thereby improving manufacturing yield and reducing manufacturing costs.
In order to achieve the foregoing object, a first silicon substrate forming a beam or a diaphragm, a probe and wiring is used for an inspection tray. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the first substrate. To position the probe having the wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or groove is formed in each of the substrates. More specifically, the projection or groove should be preferably formed by silicon anisotropic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.
The two substrates may be formed by juncture. In this case, silicon materials having equal thermal expansion coefficients are most suitable. However, the invention permits the use of other materials having thermal expansion coefficients substantially equal to that of silicon, e.g., a glass substrate developed for a micro-machine, having a thermal expansion coefficient substantially equal to that of the silicon, and enabling anodic bonding, or other resin materials. The invention also permits the use of a shape memory alloy partially joined to the first substrate.
The use of the foregoing structure enables accurate and quick inspection to be carried out. As a result, it is possible to inexpensively provide a semiconductor element or electronic components.